1. Field of Invention
The present disclosure of invention relates to a timing controller and a display apparatus having the same. More particularly, the present disclosure relates to a timing controller capable of reducing consumption of power by a memory unit through which data continuously flows and a display apparatus having the timing controller.
2. Description of Related Technology
In general, a liquid crystal display (LCD) includes two display substrates and a liquid crystal material layer interposed between the two display substrates. The LCD is structured to apply electric fields to the liquid crystal material layer to control the transmittance of light passing through the liquid crystal material layer by adjusting intensity of the electric field in different pixel areas of the LCD, thereby displaying desired images.
Recently, LCD's have found wide usage as display apparatuses in many fields such as in computers, television sets or the like to display moving images. However, a conventional LCD is not suitable for displaying fast moving images since the response speed of the liquid crystal material is often relatively slow.
Each pixel in an LCD may be modeled as including a capacitor formed by a pixel electrode, a common electrode and the liquid crystal material disposed therebetween. A predetermined time is often required in order to charge the liquid crystal capacitor to a desired target voltage with use of that same voltage and to maintain that voltage for sufficient time so as to obtain a desired light transmittance due to the slow response speed of the liquid crystal. Especially, in case that a large voltage difference exists between a previous voltage charged into the liquid crystal capacitor during a previous image frame and the target voltage corresponding to a present frame, the liquid crystal capacitor is often not charged to the target voltage during a 1 H line scanning period even if the target voltage is applied to the liquid crystal capacitor from the beginning of the horizontal line scanning period (1 H period) when the switching element of the pixel is turned on.
Accordingly, in order to speed up the response speed of the liquid crystal, one class of conventional LCD designs employs a dynamic capacitance compensation (DCC) method. According to the DCC method, compensation data voltages rather than target voltages are applied to pixels during a present frame based on a gray scale difference found between a present image data of the given pixel in present frame and a previous image data of the same pixel in a previous frame in order to speed up the response speed of the liquid crystal.
However, additional memories are necessary in the conventional LCD designs employing this DCC method to store the image data corresponding to each frame. In other words, all the image data of a previous frame is flowed into a memory that retains previous frame data in order to allow calculation of the per pixel difference relative to pixel values to be attained in a current frame. The number and size of the memories needed for such retention of old frame data depend on the number of bits per pixel of the image data and the number of pixels per frame. The data throughput speed of the old frame retaining memory depends on the number of bits per frame multiplied by the number of frames displayed per unit of time (i.e., per second). However, in the conventional LCD design, the total number of bits per frame of the image data and the number of bits per discrete pixel (e.g., 24 bits/pixel) generally do not correspond to a standard data bus widths as used in general computing applications (i.e., 16 bits per data port or 32 bits per port or 64 bits per port) and some input parts or output parts of data buses of the memory, if standard sized for general computation use, become redundant (not used). This is especially true if a same DRAM memory bank is used both for computation and display purposes although perhaps not both at the same time.